As the cost of shrinking CMOS devices continues to increase, alternative approaches, such as extending the integration of circuits into the third dimension or semiconductor substrate stacking are being explored. Thinned substrates connected by TSVs can reduce the height and width of a packaged chip stack relative to current wire bonding technologies. Performance may also be enhanced because of TSV implementation in stacked chip designs.
Several methods of producing stacked substrates and TSVs have been implemented; including stacking wafers back-to-back, back-to-front, front-to-front, and chip stacking, for example. One known method of producing front-to-front stacks may include forming the TSV structures at the first interconnect level of the front end of line (FEOL) process. The method may include patterning and etching connecting vias into the backside of the wafer after thinning. One disadvantage of this method may be the difficulty of aligning a connecting via on the backside of a thinned wafer with a prior formed TSV structure. Misalignment may result in no connection to the TSV structure, or a limited connection to the TSV structure. Further, the diameter of a backside via structure employed to connect with a TSV may be smaller than the TSV. This may cause additional problems in clearing the sacrificial material from the prior formed TSV. A TSV/backside via structure may be more resistive if the sacrificial material is not sufficiently removed. Moreover, another disadvantage of the prior formed TSV is the cost of the photo procedure to pattern the backside of the wafer.